View HFBR-5963ALZ_8545259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hfbr-5963lz/alz multimode small form factor transceivers for atm, fddi, fast ethernet and sonet oc-3/sdh stm-1 with lc connector data sheet description the hfbr-5963xxz transceiver provides the system designer with a product to implement a range of solutions for multimode fi ber fast ethernet and sonet oc-3 (sdh stm-1) physical layers for atm and other services. this transceiver is supplied in the industry standard 2 x 5 dip style with an lc fi ber connector interface with an external connector shield. applications ? sonet/sdh equipment interconnect, oc-3/sdh stm-1 rate ? fast ethernet ? multimode fi ber atm backbone links features ? rohs compliant ? multisourced 2 x 5 package style ? operates with 62.5/125 mm and 50/125 mm multi- mode fi ber ? single +3.3 v power supply ? wave solder and aqueous wash process compatibility ? manufactured in an iso 9001 certifi ed facility ? full compliance with atm forum ? uni sonet oc-3 multimode fi ber physical layer speci- fi cation ? full compliance with the optical performance require- ments of the fddi pmd standard ? full compliance with the optical performance require- ments of 100base-fx version of ieee802.3u ? +3.3 v ttl signal detect output ? temperature range: 0 c to +70 c hfbr-5963lz -40 c to +85 c HFBR-5963ALZ
2 figure 1. block diagram data out signal detect data in quantizer ic led driver ic pin photodiode pre-amplifier subassembly led optical subassembly data out data in lc receptacle r x supply t x supply r x ground t x ground transmitter section the transmitter section of the hfbr-5963xxz utilizes a 1300 nm ingaasp led. this led is packaged in the optical subassembly portion of the transmitter section. it is driven by a custom silicon ic which converts diff erential pecl logic signals, ecl referenced (shifted) to a +3.3 v supply, into an analog led drive current. receiver section the receiver section of the hfbr-5963xxz utilizes an ingaas pin photodiode coupled to a custom silicon tran- simpedance preamplifi er ic. it is packaged in the optical subassembly portion of the receiver. this pin/preamplifi er combination is coupled to a custom quantizer ic which provides the fi nal pulse shaping for the logic output and the signal detect function. the data output is diff erential. the data output is pecl compat- ible, ecl referenced (shifted) to a +3.3 v power supply. the receiver outputs, data output and data out bar, are squelched at signal detect deassert. the signal detect output is single ended. the signal detect circuit works by sensing the level of the received signal and comparing this level to a reference. the sd output is +3.3 v ttl. package the overall package concept for the avago transceiver consists of three basic elements; the two optical subas- semblies, an electrical subassembly, and the housing as illustrated in the block diagram in figure 1. the package outline drawing and pin out are shown in figures 2 and 5. the details of this package outline and pin out are compliant with the multisource defi nition of the 2 x 5 dip. the low profi le of the avago transceiver design complies with the maximum height allowed for the lc connector over the entire length of the package. the optical subassemblies utilize a high-volume assembly process together with low-cost lens elements which result in a cost- eff ective building block. the electrical subassembly consists of a high volume mul- tilayer printed circuit board on which the ics and various surface-mounted passive circuit elements are attached. the receiver section includes an internal shield for the elec- trical and optical subassemblies to ensure high immunity to external emi fi elds. the outer housing including the lc ports is molded of fi lled nonconductive plastic to provide mechanical strength. the solder posts of the avago design are isolated from the internal circuit of the transceiver. the transceiver is attached to a printed circuit board with the ten signal pins and the two solder posts which exit the bottom of the housing. the two solder posts provide the primary mechanical strength to withstand the loads imposed on the transceiver by mating with the lc connector fi ber cables.
3 figure 2. pin out diagram application information the applications engineering group is available to assist you with the technical understanding and design trade- off s associated with these transceivers. you can contact them through your avago sales representative. the following information is provided to answer some of the most common questions about the use of these parts. transceiver optical power budget versus link length optical power budget (opb) is the available optical power for a fi ber optic link to accommodate fi ber cable losses plus losses due to in-line connectors, splices, optical switches, and to provide margin for link aging and unplanned losses due to cable plant reconfi guration or repair. avago led technology has produced 1300 nm led devices with lower aging characteristics than normally associated with these technologies in the industry. the industry convention is 1.5 db aging for 1300 nm leds. the 1300 nm avago leds are specifi ed to experience less than 1 db of aging over normal commercial equipment mission life periods. contact your avago sales representative for additional details. pin descriptions: pin 1 receiver signal ground v ee rx directly connect this pin to the receiver ground plane. pin 2 receiver power supply vcc rx provide +3.3 v dc via the recommended receiver power supply fi lter circuit. locate the power supply fi lter circuit as close as possible to the v cc rx pin. pin 3 signal detect sd normal optical input levels to the receiver result in a logic 1 output. low optical input levels to the receiver result in a logic 0 output. this signal detect output can be used to drive a +3.3 v ttl input on an upstream circuit, such as signal detect input or loss of signal-bar. pin 4 receiver data out bar rd- no internal terminations are provided. see recommend- ed circuit schematic. pin 5 receiver data out rd+ no internal terminations are provided. see recommend- ed circuit schematic. pin 6 transmitter power supply v cc tx provide +3.3 v dc via the recommended transmitter power supply fi lter circuit. locate the power supply fi lter circuit as close as possible to the v cc tx pin. pin 7 transmitter signal ground v ee tx directly connect this pin to the transmitter ground plane. pin 8 nc no connection. pin 9 transmitter data in td+ no internal terminations are provided. see recommend- ed circuit schematic. pin 10 transmitter data in bar td- no internal terminations are provided. see recommend- ed circuit schematic. mounting studs/solder posts the mounting studs are provided for transceiver mechani- cal attachment to the circuit board. it is recommended that the holes in the circuit board be connected to chassis ground. transmitter data in bar transmitter data in nc transmitter signal ground transmitter power supply rx tx o o o o o 1 2 3 4 5 o o o o o 10 9 8 7 6 receiver signal ground receiver power supply signal detect receiver data out bar receiver data out top view mounting studs/solder posts
4 figure 3. recommended decoupling and termination circuits o v ee r x o v cc r x o sd o rd- o rd+ z = 50 z = 50 terminate at transceiver inputs z = 50 z = 50 10 9 8 7 6 sd lvpecl v cc (+3.3 v) terminate at device inputs lvpecl v cc (+3.3 v) phy device td+ td- rd+ rd- v cc (+3.3 v) z = 50 1 2 3 4 5 td- o td+ o n/c o v ee t x o v cc t x o 1 h c2 1 h c1 c3 10 f v cc (+3.3 v) t x r x notes: c1 = c2 = c3 = 10 nf or 100 nf * loading of r1 is optional. 100 100 130 130 130 130 lvttl r1* 4.7k recommended handling precautions avago recommends that normal static precautions be taken in the handling and assembly of these transceivers to prevent damage which may be induced by electrostatic discharge (esd). the hfbr-5963xxz series of transceivers meet mil-std- 883c method 3015.4 class 2 products. care should be used to avoid shorting the receiver data or signal detect outputs directly to ground without proper current limiting impedance. solder and wash process compatibility the transceivers are delivered with protective process plugs inserted into the lc receptacle. this process plug protects the optical subassemblies during wave solder and aqueous wash processing and acts as a dust cover during shipping. these transceivers are compatible with either industry standard wave or hand solder processes. shipping container the transceiver is packaged in a shipping container designed to protect it from mechanical and esd damage during shipment or storage. board layout - decoupling circuit, ground planes and termination circuits it is important to take care in the layout of your circuit board to achieve optimum performance from these trans- ceivers. figure 3 provides a good example of a schematic for a power supply decoupling circuit that works well with these parts. it is further recommended that a con- tiguous ground plane be provided in the circuit board directly under the transceiver to provide a low inductance ground for signal return current. this recommendation is in keeping with good high frequency board layout practices. figures 3 and 4 show two recommended ter- mination schemes.
5 figure 4. alternative termination circuits o v ee r x o v cc r x o sd o rd- o rd+ z = 50 130 v cc (+3.3 v) 10 nf z = 50 130 82 82 terminate at transceiver inputs z = 50 z = 50 10 9 8 7 6 sd lvpecl v cc (+3.3 v) terminate at device inputs lvpecl v cc (+3.3 v) phy device td+ td- rd+ rd- z = 50 1 2 3 4 5 td- o td+ o n/c o v ee t x o v cc t x o 1 h c2 1 h c1 c3 10 f v cc (+3.3 v) t x r x note: c1 = c2 = c3 = 10 nf or 100 nf * loading r1 is optional. 10 nf 130 82 v cc (+3.3 v) 130 82 v cc (+3.3 v) r1* 4.7k lvttl board layout - hole pattern the avago transceiver complies with the circuit board common transceiver footprint hole pattern defi ned in the original multisource announcement which defi ned the 2 x 5 package style. this drawing is reproduced in figure 6 with the addition of ansi y14.5m compliant dimension- ing to be used as a guide in the mechanical layout of your circuit board. figure 6 illustrates the recommended panel opening and the position of the circuit board with respect to this panel. regulatory compliance these transceiver products are intended to enable commercial system designers to develop equipment that complies with the various international regula- tions governing certifi cation of information technology equipment. see the regulatory compliance table for details. additional information is available from your avago sales representative.
6 all dimensions in milimeters(inches) figure 5. package outline drawing
7 figure 6. recommended board layout hole pattern and panel mounting 2.29 (.090) 15.24 (.600) min. pitch 14.22 .10 (.560 .004) a a 0.81 .10 (.032 .004) 20 x ? 1.40 .10 (.055 .004) 4 x ? (note 5) see detail a 13.34 (.525) 12.16 (.479) 15.24 (.600) 7.59 (.299) 10.16 (.400) 4.57 (.180) 7.11 (.280) 1.78 (.070) 9 x 3.56 (.140) 5 4 3 2 1 6 7 8 9 10 see note 3 8.89 (.350) 10.16 .10 (.400 .004) top of pcb section a - a a + 1.50 - 0 (+.059) (- .000) 1.00 (.039) + 0 - 0.75 (+.000) (- .030) 15.75 (.620) detail b (4 x) 1 .039 1.8 .071 detail a (3 x) 3 (.118) 2 x ? max. (area for eyelet's) 6 (.236) 1.40 .10 (.055 .004) 2 x ? (note 4) 3 (.118) 25.75 (1.014) min. pitch see detail b electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the fi rst case is during handling of the transceiver prior to mounting it on the circuit board. it is important to use normal esd handling precautions for esd sensitive devices. these precautions include using grounded wrist straps, work benches, and fl oor mats in esd controlled areas. the second case to consider is static discharges to the exterior of the equipment chassis containing the trans- ceiver parts. to the extent that the lc connector is exposed to the outside of the equipment chassis it may be subject to whatever esd system level test criteria that the equipment is intended to meet. electromagnetic interference (emi) most equipment designs utilizing this high speed trans- ceiver from avago will be required to meet the require- ments of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. this product is suitable for use in designs ranging from a desktop computer with a single transceiver to a concen- trator or switch product with a large number of transceiv- ers. notes: 1. this page describes the recommended circuit board layout and front panel openings for sff transceivers. 2. the hatched areas are keep-out areas reserved for housing standoffs. no metal traces allowed in keep-out areas. 3. this drawing shows extra pin holes for 2 x 6 pin and 2 x 10 pin transceivers. these extra holes are not required for hfbr-59 61xxz and other 2 x 5 pin sff modules. 4. holes for mounting studs must not be tied to signal ground but may be tied to chassis ground. 5. holes for housing leads optional and not required for hfbr--5963xxz. if needed in future, these holes must be tied to signal ground. 6. all dimensions are in millimeters (inches).
8 regulatory compliance feature test method performance electrostatic discharge (esd) to the electrical pins mil-std-883c meets class 2 (2000 to 3999 volts).withstand up to 2200 v applied between electrical pins. electrostatic discharge (esd) to the lc receptacle variation of iec 61000-4-2 typically withstand at least 25 kv without damage when the lc connector receptacle is contacted by a human body model probe. electromagnetic interfer- ence (emi) fcc class b cenelec cen55022 vcciclass 2 transceivers typically provide a 10 db margin to the noted standard limits when tested at a certifi ed test range with the transceiver mounted to a circuit card without a chassis enclosure. immunity variation of iec 61000-4-3 typically show no measurable eff ect from a 10 v/m fi eld swept from 80 to 450 mhz applied to the transceiver when mounted to a circuit card withouta chassis enclosure. eye safety ael class 1en60825-1 (+a11) compliant per avago testing under single fault conditions. tuv certifi cation: r 02071015 component recognition underwriters laboratories and ca- nadian standards association joint component recognition for informa- tion technology equipment including electrical business equipment ul file #: e173874 200 100 c C transmitter output optical rise/fall times C ns 1280 1300 1320 180 160 140 120 1360 1340 ? - transmitter output optical spectral width (fwhm) - nm 1.0 1.5 2.5 3.0 2.0 hfbr-5961xxz transmitter test results of c , ? and t r/f 1260 t r/f C transmitter output optical rise/ fall times C ns 3.0 are correlated and comply with the allowed spectral width as a function of center wavelength for various rise and fall times. 0 1 2 3 4 5 6 -3 -2 -1 0 1 2 3 eye sampling time position (ns) relative input optical power (db) conditions: 1. t a = +25 c 2. v cc = 3.3 v dc 3. input optical rise/ fall times = 2.1/1.9 ns. 4. input optical power is normalized to center of data symbol. 5. note 15 and 16 apply. immunity equipment utilizing these transceivers will be subject to radio-frequency electromagnetic fi elds in some environ- ments these transceivers have a high immunity to such fi elds. for additional information regarding emi, susceptibility, esd and conducted noise testing procedures and results refer to application note 1166: minimizing radiated emissions of high-speed data communications systems. transceiver reliability and performance qualifi cation data the 2 x 5 transceivers have passed avago reliability and performance qualifi cation testing and are undergoing ongoing quality and reliability monitoring. details are available from your avago sales representative. these transceivers are manufactured at the avago singapore location which is an iso 9001 certifi ed facility. applications support materials contact your local avago component field sales offi ce for information on how to obtain pcb layouts and evalua- tion boards for the 2 x 5 transceivers. figure 7. transmitter output optical spectral width (fwhm) vs. transmitter output optical center wavelength and rise/fall times. figure 8. relative input optical power vs. eye sampling time position.
9 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. it should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. exposure to the absolute maximum ratings for extended periods can adversely aff ect device reliability. parameter symbol minimum typical maximum units notes storage temperature t s -40 +100 c lead soldering temperature t sold +260 c lead soldering time t sold 10 sec supply voltage v cc -0.5 3.63 v data input voltage v i -0.5 v cc v diff erential input voltage (p-p) v d 2.0 v 1 output current i o 50 ma parameter symbol minimum typical maximum units notes case operating temperature hfbr-5963lz HFBR-5963ALZ t c t c 0 -40 +70 +85 c c supply voltage v cc 2.97 3.3 3.63 v data input voltage - low v il - v cc -1.810 -1.475 v data input voltage - high v ih - v cc -1.165 -0.880 v data and signal detect output load r l 50 ? 2 diff erential input voltage (p-p) v d 0.800 v parameter symbol minimum typical maximum units notes supply current i cc 110 175 ma 3 power dissipation p diss 0.4 0.64 w 5a data input current - low i il -350 -2 a data input current - high i ih 18 350 a transmitter electrical characteristics hfbr-5963lz (t c = 0 oc to +70 oc, v cc =2.97 v to 3.63 v) HFBR-5963ALZ (t c = -40 oc to +85 oc, v cc =2.97 v to 3.63v) recommended operating conditions
10 receiver electrical characteristics hfbr-5963lz (t c = 0 oc to +70 oc, v cc = 2.97v to 3.63 v) HFBR-5963ALZ (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) parameter symbol minimum typical maximum units notes supply current i cc 65 120 ma 4 power dissipation p diss 0.225 0.44 w 5b data output voltage - low v ol - v cc -1.840 -1.620 v 6 data output voltage - high v oh - v cc -1.045 -0.880 v 6 data output rise time t r 0.35 2.2 ns 7 data output fall time t f 0.35 2.2 ns 7 signal detect output voltage - low sdv ol 0.6 v 6 signal detect output voltage - high sdv oh 2.2 v 6 power supply noise rejection psnr 50 mv parameter symbol minimum typical maximum units notes output optical power bol 62.5/125 m, na = 0.275 fiber eol p o -19 -20 -15.7 -14 dbm avg 8 output optical power bol 50/125 m, na = 0.20 fiber eol p o -22.5 -23.5 -14 dbm avg 8 optical extinction ratio 0.002 -47 0.2 -27 % db 9 output optical power at logic low 0 state p o (0) -45 dbm avg 10 center wavelength ? c 1270 1308 1380 nm 23, figure 7 spectral width - fwhm spectral width - rms ?? 147 63 nm 11, 23 figure 7 optical rise time t r 0.6 2.1 3.0 ns 12, 23 figure 7 optical fall time t f 0.6 1.9 3.0 ns 12, 23 figure 7 systematic jitter contributed by the transmitter oc-3 sj 0.4 1.2 ns p-p 13a duty cycle distortion contributed by the trans- mitter fe dcd 0.36 0.6 ns p-p 13b data dependent jitter contributed by the transmitter fe ddj 0.07 0.6 ns p-p 13c random jitter contributed by the transmitter oc-3 fe rj 0.1 0.1 0.52 0.69 ns p-p 14a 14b transmitter optical characteristics hfbr-5963lz (t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) HFBR-5963ALZ (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v)
11 receiver optical and electrical characteristics hfbr-5963lz (t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) HFBR-5963ALZ (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) notes: 1. this is the maximum voltage that can be applied across the diff er- ential transmitter data inputs to prevent damage to the input esd protection circuit. 2. the data outputs are terminated with 50 ? connected to v cc C 2 v. the signal detect output is terminated with 50 ? connected to a pull-up resistor of 4.7 k ? tied to v cc . 3. the power supply current needed to operate the transmitter is provided to diff erential ecl circuitry. this circuitry maintains a nearly constant current fl ow from the power supply. constant current operation helps to prevent unwanted electrical noise from being generated and conducted or emitted to neighboring circuitry. 4. this value is measured with the outputs terminated into 50 ? connected to v cc C 2v and an input optical power level of C14 dbm average. 5a. the power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current. 5b. the power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus the sum of the products of the output voltages and currents. 6. the data output low and high voltages are measured with respect to v cc with the output terminated into 50 ? connected to v cc C 2 v. 7. the data output rise and fall times are measured between 20% and 80% levels with the output connected to v cc C 2v through 50 ? . 8. these optical power values are measured with the following con- ditions: the beginning of life (bol) to the end of life (eol) optical power degradation is typically 1.5 db per the industry convention for long wavelength leds. the actual degradation observed in avagos parameter symbol minimum typical maximum units notes input optical power at minimum at window edge oc-3 fe p in min (w) -30 -31 dbm avg 15a, figure 8 15b input optical power at eye center oc-3 fe p in min (c) -31 -31.8 dbm avg 16a, figure 8 16b input optical power maximum oc-3 fe p in max -14 -14 dbm avg 15a 15b operating wavelength ? 1270 1380 nm systematic jitter contributed by the receiver oc-3 sj 0.2 1.2 ns p-p 17a duty cycle distortion contributed by the receiver fe dcd 0.08 0.4 ns p-p 17b data dependent jitter contributed by the receiver fe ddj 0.07 1.0 ns p-p 17c random jitter contributed by the receiver oc-3 fe rj 0.3 0.3 1.91 2.14 ns p-p 18a 18b signal detect - asserted oc-3 fe p a p d + 1.5 db -31-33 dbm avg 19 signal detect - deasserted p d -45 dbm avg 20 signal detect - hysteresis p a - p d 1.5 db signal detect assert time (off to on) 0 2 100 s 21 signal detect deassert time (on to off ) 0 5 100 s 22 1300 nm led products is < 1db, as specifi ed in this data sheet. over the specifi ed operating voltage and temper ature ranges. with 25 mbd (12.5 mhz square-wave), input signal. at the end of one meter of noted optical fi ber with cladding modes removed. the average power value can be converted to a peak power value by adding 3 db. higher output optical power transmitters are available on special request. please consult with your local avago sales representative for further details. 9. the extinction ratio is a measure of themodulation depth of the optical signal. the data 0 output optical power is compared to the data 1 peak output optical power and expressed as a percent- age. with the transmitter driven by a 25 mbd (12.5 mhz square- wave) input signal, the average optical power is measured. the data 1 peak power is then calculated by adding 3 db to the measured average optical power. the data 0 output optical power is found by measuring the optical power when the transmitter is driven by a logic 0 input. the extinction ratio is the ratio of the optical power at the 0 level compared to the optical power at the 1 level expressed as a percentage or in decibels. 10. the transmitter will provide this low level of output optical power when driven by a logic 0 input. this can be useful in link trouble- shooting. 11. the relationship between full width half maximum and rms values for spectral width is derived from the assumption of a gaussian shaped spectrum which results in a 2.35 x rms = fwhm relation- ship.
12 12. the optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 mbd (12.5 mhz square-wave) input signal. the ansi t1e1.2 committee has designated the possibility of defi ning an eye pattern mask for the transmitter optical output as an item for further study. avago will incorporate this requirement into the specifi cations for these products if it is defi ned. the hfbr- 59xxl products typically comply with the template requirements of ccitt (now itu-t) g.957 section 3.2.5, figure 5 for the stm- 1 rate, excluding the optical receiver fi lter normally associated with single mode fi ber measurements which is the likely source for the ansi t1e1.2 committee to follow in this matter. 13a. systematic jitter contributed by the transmitter is defi ned as the combination of duty cycle distortion and data dependent jitter. systematic jitter is measured at 50% threshold using a 155.52 mbd (77.5 mhz square-wave), 2 23 -1 psuedorandom data pattern input signal. 13b. duty cycle distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal using an idle line state, 125 mbd (62.5 mhz square-wave), input signal. 13c. data dependent jitter contributed by the transmitter is specifi ed with the fddi t est pattern described in fddi pmd annex a.5. 14a. random jitter contributed by the transmitter is specifi ed with a 155.52 mbd (77.5 mhz square-wave) input signal. 14b. random jitter contributed by the transmitter is specifi ed with an idle line state, 125 mbd (62.5 mhz square-wave), input signal. see application information - transceiver jitter performance section of this data sheet for further details. 15a. this specifi cation is intended to indicate the performance of the receiver section of the transceiver when input optical power signal characteristics are present per the at the beginning of life (bol) over the specifi ed operating tempera ture and voltage ranges 23 input is a 155.52 mbd, 2 - 1 prbs data pattern with 72 1 s and 72 0s inserted per the ccitt (now itu-t) recommendation g.958 appendix i. receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. the actual test data window time- width is set to simulate the eff ect of worst case optical input jitter based on the transmitter jitter values from the specifi cation tables. the test window time-width is hfbr-5963l 3.32 ns. transmitter operating with a 155.52 mbd, 77.5 mhz square-wave, input signal to simulate any cross-talk present between the trans- mitter and receiver sections of the transceiver. 15b. this specifi cation is intended to indicate the performance of the receiver section of the transceiver when input optical power signal characteristics are present per the following defi nitions. the input optical power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a bit error rate (ber) better than or equal to 2.5 x 10 -10 . ? at the beginning of life (bol) ? over the specifi ed operating temperature and voltage ranges ? input symbol pattern is the fddi t est pattern defi ned in fddi pmd annex a.5 with 4b/5b nrzi encoded data that contains a duty cycle base-line wander eff ect of 50 khz. this sequence causes a near worst case condition for inter-symbol interference. ? receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. this worst case window time-width is the minimum allowed eye-opening presented to the fddi phy pm_data indica- tion input (phy input) per the example in fddi pmd annex e. this minimum window time-width of 2.13 ns is based upon the worst case fddi pmd active input interface optical conditions for peak- to-peak dcd (1.0 ns), ddj (1.2 ns) and rj (0.76 ns) presented to the receiver. to test a receiver with the worst case fddi pmd active input jitter condition requires exacting control over dcd, ddj and rj jitter compo nents that is diffi cult to implement with production test equipment. the re ceiver can be equivalently tested to the worst case fddi pmd input jitter conditions and meet the minimum output data window time-width of 2.13 ns. this is accom plished by using a nearly ideal input optical signal (no dcd, insignifi cant ddj and rj) and measuring for a wider window time-width of 4.6 ns. this is possible due to the cumula tive eff ect of jitter components through their superposition (dcd and ddj are directly additive and rj com- ponents are rms additive). specifi cally, when a nearly ideal input optical test signal is used and the maximum receiver peak-to-peak jitter contributions of dcd (0.4 ns), ddj (1.0 ns), and rj (2.14 ns) exist, the minimum window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. this wider window time-width of 4.6 ns guarantees the fddi pmd annex e minimum window time-width of 2.13 ns under worst case input jitter condi- tions to the avago receiver. ? transmitter operating with an idle line state pattern, 125 mbd (62.5 mhz square-wave), input signal to simulate any cross-talk present between the trans mit t er and receiver sections of the transceiver. 16a. all conditions of note 15a apply except that the measurement is made at the center of the symbol with no window time- width. 16b. all conditions of note 15b apply except that the measurement is made at the center of the symbol with no window time-width. 17a. systematic jitter contributed by the receiver is defi ned as the com- bination of duty cycle distortion and data dependent jitter. sys- tematic jitter is measured at 50% threshold using a 155.52 mbd (77.5 mhz square- wave), 2 23 - 1 psuedorandom data pattern input signal. 17b. duty cycle distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an idle line state, 125 mbd (62.5 mhz square-wave), input signal. the input optical power level is -20 dbm average. 17c. data dependent jitter contributed by the receiver is specifi ed with the fddi ddj test pattern described in the fddi pmd annex a.5. the input optical power level is -20 dbm average. 18a. random jitter contributed by the receiver is specifi ed with a 155.52 mbd (77.5 mhz square- wave) input signal. 18b. random jitter contributed by the receiver is specifi ed with an idle line state, 125 mbd (62.5 mhz square-wave), input signal. the input optical power level is at maxi mum p in min. (w). see applica tion in- formation - transceiver jitter section for further information. 19. this value is measured during the transition from low to high levels of input optical power. 20. this value is measured during the transition from high to low levels of input optical power. at signal detect deassert, the receiver outputs data out and data out bar go to steady pecl levels high and low respectively. 21. the signal detect output shall be asserted within 100 us after a step increase of the input optical power. 22. signal detect output shall be de-asserted within 100 s after a step decrease in the input optical power. at signal detect deassert, the receiver outputs data out and data out bar go to steady pecl levels high and low respectively. 23. the hfbr-5963l transceiver complies with the requirements for the trade-off s between center wavelength, spectral width, and rise/fall times shown in figure 7. this fi gure is derived from the fddi pmd standard (iso/iec 9314-3 : 1990 and ansi x3.166 - 1990) per the de- scription in ansi t1e1.2 revision 3. the interpretation of this fi gure is that values of center wavelength and spectral width must lie along the appropriate optical rise/fall time curve.
ordering information 1300 nm led (operating case temperature 0 to +70 c) hfbr-5963lz 1300 nm led (operating case temperature -40 to +85 c) HFBR-5963ALZ for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. obsoletes 5989-4768en av02-1088en - january 13, 2012

▲Up To Search▲

Price & Availability of HFBR-5963ALZ

	To Download HFBR-5963ALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .